1. Field of the Invention
The present invention relates to a semiconductor wafer and a semiconductor device. Further, the present invention relates to a method of manufacturing a semiconductor device.
2. Description of Related Art
Semiconductor wafers are partitioned into a plurality of element forming regions by a scribe line region. Semiconductor chips are obtained by dicing each semiconductor wafer along the scribe line region in an assembly and testing process. A dicing process is carried out by cutting the semiconductor wafer with a blade or the like. In this case, damage may occur in the scribe line region and the damage may spread to the element forming region.
If the damage spreads to the element forming region, the reliability of the semiconductor chip inevitably deteriorates. In view of this, a technique is proposed in which the deterioration in reliability of a semiconductor device due to the damage occurring in the scribe line region during the dicing process is suppressed.
FIG. 12 shows a partially enlarged plan view of a semiconductor wafer 150 disclosed in Japanese Unexamined Patent Application Publication No. 2006-108489. FIG. 13 shows a cross-sectional view taken along the line XIII-XIII of FIG. 12. As shown in FIG. 12, the semiconductor wafer 150 includes a plurality of rectangular semiconductor chip regions 102, and a scribe line region 101 surrounding the semiconductor chip regions 102. Further, the semiconductor wafer 150 includes a first interlayer insulating film 140, a diffusion preventing film 141, a low-dielectric-constant film 142, and a passivation film 110, which are stacked on a semiconductor substrate 145 (see FIG. 13).
Referring to FIG. 12, in the vicinity of a boundary with the semiconductor chip regions 102 in the scribe line region 101, endless trenches 107 and 108 are formed to surround the semiconductor chip regions 102. Referring to FIG. 13, the trenches 107 and 108 are isolation trenches that penetrate the films to reach the surface of the semiconductor substrate 145. Further, a metal pattern 130 of a pad for a test element group (TEG) is formed in a Y-axis direction of FIG. 12 in the scribe line region 101.
The semiconductor wafer 150 having the above structure is diced along the scribed line region 101 in an X-axis direction by using a blade device (not shown) so that the trench 107 formed in the X-axis direction is included on the side of the semiconductor chip regions. After that, the semiconductor wafer 150 is diced along the scribe line region 101 in the Y-axis direction so that the trench 108 formed in the Y-axis direction is included on the side of the semiconductor chip regions. Japanese Unexamined Patent Application Publication No. 2006-108489 discloses a technique capable of preventing the damage occurring during the dicing process from spreading to the semiconductor chip regions 102, by providing the trenches 107 and 108, each of which has a depth at which the surface of the semiconductor substrate 145 is exposed, in the vicinity of the semiconductor chip regions 102.
FIG. 14 is a partially enlarged cross-sectional view of a semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2006-140404. A semiconductor device 152 includes a copper interconnection 130, an interlayer connection portion 131, low-dielectric-constant films 132a to 132c, silicon oxide films 133 and 134, a surface protection film 110a, a sealing ring 109, and a trench portion 107a. 
Referring to FIG. 14, the trench portion 107a is formed so that a region in which the silicon oxide film 133 is reduced in thickness is formed outside the sealing ring 109. Japanese Unexamined Patent Application Publication No. 2006-140404 discloses a technique capable of preventing peeling due to the damage occurring during the dicing process from spreading to the sealing ring 109 even when a chipping 139 occurs at an end face of the silicon substrate 145a due to a mechanical strength applied during the dicing process.
Japanese Unexamined Patent Application Publication No. 2006-203215 does not disclose the technique of preventing the damage occurring in the scribe line region during the dicing process, but discloses a structure in which openings are formed in a passivation film at both ends of a scribe line region, that is, at a boundary with a chip region so as to surround the chip region. FIG. 15 is a cross-sectional view showing a main part of a semiconductor integrated circuit device (semiconductor wafer) 150b having not been diced yet as disclosed in Japanese Unexamined Patent Application Publication No. 2006-203215. The semiconductor wafer 150b includes a semiconductor chip region 102b having a plurality of elements formed on a semiconductor substrate (not shown), and a scribe line region 101b surrounding the semiconductor chip region 102b. 
In the scribe line region 101b, a metal film 130b and a passivation film 110b are formed on an insulating layer 140 formed of a silicon oxide film. In the passivation film 110b, an endless trench 107b is formed to surround the semiconductor chip region 102b. 
To meet recent demand for a chip shrink, the width of the scribe line region has been reduced. As a result, a margin between a dicing-cut surface and an element forming region is reduced, and the damage occurring in the scribe line region during the dicing process is more likely to spread to the semiconductor chip region than before. Accordingly, there is a strong demand for a technique of providing a semiconductor device with high reliability to cope with the reduction in width of the scribe line region.
Japanese Unexamined Patent Application Publication No. 2006-108489 discloses the structure in which the endless trenches 107 and 108 that penetrate the films to reach the surface of the semiconductor substrate 145 are formed, which results in an undesirable increase in etching time when the trenches are formed by etching. Further, there is such a limitation that the metal pattern 130 provided in the scribe line region has to be formed within a region between the trenches 108.
Japanese Unexamined Patent Application Publication No. 2006-140404 discloses means effectively used as a method of preventing a crack from occurring in the sealing ring in the semiconductor device having the low-dielectric-constant films, but does not disclose any method of providing a semiconductor device capable of coping with the reduction in width of the scribe line region.
Japanese Unexamined Patent Application Publication No. 2006-203215 discloses the structure for eliminating a failure caused during a bump forming process, but does not disclose any method of providing a semiconductor device capable of coping with the reduction in width of the scribe line region.